From 1905b40f1bf9d2f332d1f545ed836705cb1c603b Mon Sep 17 00:00:00 2001 From: Rerumu Date: Thu, 18 Nov 2021 00:13:36 -0500 Subject: [PATCH] Refactor visitors --- src/backend/translator/level_2.rs | 6 +- src/backend/visitor/memory.rs | 2 +- src/backend/visitor/register.rs | 295 ++++++++++++------------------ 3 files changed, 124 insertions(+), 179 deletions(-) diff --git a/src/backend/translator/level_2.rs b/src/backend/translator/level_2.rs index 0416b79..6effeb0 100644 --- a/src/backend/translator/level_2.rs +++ b/src/backend/translator/level_2.rs @@ -6,7 +6,7 @@ use crate::{ backend::{ edition::data::Edition, helper::writer::{write_ordered, Writer}, - visitor::{memory::visit_for_memory, register::visit_for_register}, + visitor::{memory, register}, }, data::Module, }; @@ -58,8 +58,8 @@ fn gen_memory(set: BTreeSet, w: Writer) -> Result<()> { } pub fn gen_function(spec: &dyn Edition, index: usize, m: &Module, w: Writer) -> Result<()> { - let mem_set = visit_for_memory(m, index); - let num_stack = visit_for_register(m, index); + let mem_set = memory::visit(m, index); + let num_stack = register::visit(m, index); let num_param = m.in_arity[index].num_param; let num_local = m.code[index].num_local; diff --git a/src/backend/visitor/memory.rs b/src/backend/visitor/memory.rs index c41c1a9..3ffd20f 100644 --- a/src/backend/visitor/memory.rs +++ b/src/backend/visitor/memory.rs @@ -4,7 +4,7 @@ use parity_wasm::elements::Instruction; use crate::data::Module; -pub fn visit_for_memory(m: &Module, index: usize) -> BTreeSet { +pub fn visit(m: &Module, index: usize) -> BTreeSet { let mut result = BTreeSet::new(); for i in m.code[index].inst_list { diff --git a/src/backend/visitor/register.rs b/src/backend/visitor/register.rs index 7b12c82..b5aaca4 100644 --- a/src/backend/visitor/register.rs +++ b/src/backend/visitor/register.rs @@ -5,7 +5,7 @@ use crate::{ data::{Arity, Module}, }; -pub fn visit_for_register(m: &Module, index: usize) -> u32 { +pub fn visit(m: &Module, index: usize) -> u32 { let mut reg = Register::new(); let num_param = m.in_arity[index].num_param; let num_local = m.code[index].num_local; @@ -28,7 +28,11 @@ pub fn visit_for_register(m: &Module, index: usize) -> u32 { Instruction::End => { reg.load(); } - Instruction::BrIf(_) | Instruction::BrTable(_) => { + Instruction::BrIf(_) + | Instruction::BrTable(_) + | Instruction::Drop + | Instruction::SetLocal(_) + | Instruction::SetGlobal(_) => { reg.pop(1); } Instruction::Call(i) => { @@ -44,30 +48,21 @@ pub fn visit_for_register(m: &Module, index: usize) -> u32 { reg.pop(arity.num_param + 1); reg.push(arity.num_result); } - Instruction::Drop => { - reg.pop(1); - } Instruction::Select => { reg.pop(3); reg.push(1); } - Instruction::GetLocal(_) => { + Instruction::GetLocal(_) + | Instruction::GetGlobal(_) + | Instruction::CurrentMemory(_) + | Instruction::I32Const(_) + | Instruction::I64Const(_) + | Instruction::F32Const(_) + | Instruction::F64Const(_) => { reg.push(1); } - Instruction::SetLocal(_) => { - reg.pop(1); - } - Instruction::TeeLocal(_) => { - reg.pop(1); - reg.push(1); - } - Instruction::GetGlobal(_) => { - reg.push(1); - } - Instruction::SetGlobal(_) => { - reg.pop(1); - } - Instruction::I32Load(_, _) + Instruction::TeeLocal(_) + | Instruction::I32Load(_, _) | Instruction::I64Load(_, _) | Instruction::F32Load(_, _) | Instruction::F64Load(_, _) @@ -80,171 +75,33 @@ pub fn visit_for_register(m: &Module, index: usize) -> u32 { | Instruction::I64Load16S(_, _) | Instruction::I64Load16U(_, _) | Instruction::I64Load32S(_, _) - | Instruction::I64Load32U(_, _) => { - reg.pop(1); - reg.push(1); - } - Instruction::I32Store(_, _) - | Instruction::I64Store(_, _) - | Instruction::F32Store(_, _) - | Instruction::F64Store(_, _) - | Instruction::I32Store8(_, _) - | Instruction::I32Store16(_, _) - | Instruction::I64Store8(_, _) - | Instruction::I64Store16(_, _) - | Instruction::I64Store32(_, _) => { - reg.pop(2); - } - Instruction::CurrentMemory(_) => { - reg.push(1); - } - Instruction::GrowMemory(_) => { - reg.pop(1); - reg.push(1); - } - Instruction::I32Const(_) - | Instruction::I64Const(_) - | Instruction::F32Const(_) - | Instruction::F64Const(_) => { - reg.push(1); - } - Instruction::I32Eqz => { - reg.pop(1); - reg.push(1); - } - Instruction::I32Eq - | Instruction::I32Ne - | Instruction::I32LtS - | Instruction::I32LtU - | Instruction::I32GtS - | Instruction::I32GtU - | Instruction::I32LeS - | Instruction::I32LeU - | Instruction::I32GeS - | Instruction::I32GeU => { - reg.pop(2); - reg.push(1); - } - Instruction::I64Eqz => { - reg.pop(1); - reg.push(1); - } - Instruction::I64Eq - | Instruction::I64Ne - | Instruction::I64LtS - | Instruction::I64LtU - | Instruction::I64GtS - | Instruction::I64GtU - | Instruction::I64LeS - | Instruction::I64LeU - | Instruction::I64GeS - | Instruction::I64GeU - | Instruction::F32Eq - | Instruction::F32Ne - | Instruction::F32Lt - | Instruction::F32Gt - | Instruction::F32Le - | Instruction::F32Ge - | Instruction::F64Eq - | Instruction::F64Ne - | Instruction::F64Lt - | Instruction::F64Gt - | Instruction::F64Le - | Instruction::F64Ge => { - reg.pop(2); - reg.push(1); - } - Instruction::I32Clz | Instruction::I32Ctz | Instruction::I32Popcnt => { - reg.pop(1); - reg.push(1); - } - Instruction::I32Add - | Instruction::I32Sub - | Instruction::I32Mul - | Instruction::I32DivS - | Instruction::I32DivU - | Instruction::I32RemS - | Instruction::I32RemU - | Instruction::I32And - | Instruction::I32Or - | Instruction::I32Xor - | Instruction::I32Shl - | Instruction::I32ShrS - | Instruction::I32ShrU - | Instruction::I32Rotl - | Instruction::I32Rotr => { - reg.pop(2); - reg.push(1); - } - Instruction::I64Clz | Instruction::I64Ctz | Instruction::I64Popcnt => { - reg.pop(1); - reg.push(1); - } - Instruction::I64Add - | Instruction::I64Sub - | Instruction::I64Mul - | Instruction::I64DivS - | Instruction::I64DivU - | Instruction::I64RemS - | Instruction::I64RemU - | Instruction::I64And - | Instruction::I64Or - | Instruction::I64Xor - | Instruction::I64Shl - | Instruction::I64ShrS - | Instruction::I64ShrU - | Instruction::I64Rotl - | Instruction::I64Rotr => { - reg.pop(2); - reg.push(1); - } - Instruction::F32Abs + | Instruction::I64Load32U(_, _) + | Instruction::GrowMemory(_) + | Instruction::I32Eqz + | Instruction::I64Eqz + | Instruction::I32Clz + | Instruction::I32Ctz + | Instruction::I32Popcnt + | Instruction::I64Clz + | Instruction::I64Ctz + | Instruction::I64Popcnt + | Instruction::F32Abs | Instruction::F32Neg | Instruction::F32Ceil | Instruction::F32Floor | Instruction::F32Trunc | Instruction::F32Nearest - | Instruction::F32Sqrt => { - reg.pop(1); - reg.push(1); - } - Instruction::F32Add - | Instruction::F32Sub - | Instruction::F32Mul - | Instruction::F32Div - | Instruction::F32Min - | Instruction::F32Max => { - reg.pop(2); - reg.push(1); - } - Instruction::F32Copysign => { - reg.pop(1); - reg.push(1); - } - Instruction::F64Abs + | Instruction::F32Sqrt + | Instruction::F32Copysign + | Instruction::F64Abs | Instruction::F64Neg | Instruction::F64Ceil | Instruction::F64Floor | Instruction::F64Trunc | Instruction::F64Nearest - | Instruction::F64Sqrt => { - reg.pop(1); - reg.push(1); - } - Instruction::F64Add - | Instruction::F64Sub - | Instruction::F64Mul - | Instruction::F64Div - | Instruction::F64Min - | Instruction::F64Max => { - reg.pop(2); - reg.push(1); - } - Instruction::F64Copysign => { - reg.pop(1); - reg.push(1); - } - Instruction::I32WrapI64 + | Instruction::F64Sqrt + | Instruction::F64Copysign + | Instruction::I32WrapI64 | Instruction::I32TruncSF32 | Instruction::I32TruncUF32 | Instruction::I32TruncSF64 @@ -272,6 +129,94 @@ pub fn visit_for_register(m: &Module, index: usize) -> u32 { reg.pop(1); reg.push(1); } + Instruction::I32Store(_, _) + | Instruction::I64Store(_, _) + | Instruction::F32Store(_, _) + | Instruction::F64Store(_, _) + | Instruction::I32Store8(_, _) + | Instruction::I32Store16(_, _) + | Instruction::I64Store8(_, _) + | Instruction::I64Store16(_, _) + | Instruction::I64Store32(_, _) => { + reg.pop(2); + } + Instruction::I32Eq + | Instruction::I32Ne + | Instruction::I32LtS + | Instruction::I32LtU + | Instruction::I32GtS + | Instruction::I32GtU + | Instruction::I32LeS + | Instruction::I32LeU + | Instruction::I32GeS + | Instruction::I32GeU + | Instruction::I64Eq + | Instruction::I64Ne + | Instruction::I64LtS + | Instruction::I64LtU + | Instruction::I64GtS + | Instruction::I64GtU + | Instruction::I64LeS + | Instruction::I64LeU + | Instruction::I64GeS + | Instruction::I64GeU + | Instruction::F32Eq + | Instruction::F32Ne + | Instruction::F32Lt + | Instruction::F32Gt + | Instruction::F32Le + | Instruction::F32Ge + | Instruction::F64Eq + | Instruction::F64Ne + | Instruction::F64Lt + | Instruction::F64Gt + | Instruction::F64Le + | Instruction::F64Ge + | Instruction::I32Add + | Instruction::I32Sub + | Instruction::I32Mul + | Instruction::I32DivS + | Instruction::I32DivU + | Instruction::I32RemS + | Instruction::I32RemU + | Instruction::I32And + | Instruction::I32Or + | Instruction::I32Xor + | Instruction::I32Shl + | Instruction::I32ShrS + | Instruction::I32ShrU + | Instruction::I32Rotl + | Instruction::I32Rotr + | Instruction::I64Add + | Instruction::I64Sub + | Instruction::I64Mul + | Instruction::I64DivS + | Instruction::I64DivU + | Instruction::I64RemS + | Instruction::I64RemU + | Instruction::I64And + | Instruction::I64Or + | Instruction::I64Xor + | Instruction::I64Shl + | Instruction::I64ShrS + | Instruction::I64ShrU + | Instruction::I64Rotl + | Instruction::I64Rotr + | Instruction::F32Add + | Instruction::F32Sub + | Instruction::F32Mul + | Instruction::F32Div + | Instruction::F32Min + | Instruction::F32Max + | Instruction::F64Add + | Instruction::F64Sub + | Instruction::F64Mul + | Instruction::F64Div + | Instruction::F64Min + | Instruction::F64Max => { + reg.pop(2); + reg.push(1); + } _ => {} } }